Jensen Huang flew to Taiwan over the holiday weekend, a week ahead of his June 1 Computex keynote, to sit across the table from TSMC chairman C.C. Wei. The agenda was not the keynote slides. The agenda was advanced packaging capacity for the Vera Rubin platform, the chip system Huang has been calling, in his usual restrained way, “the largest product launch, probably in the history of Taiwan.”
The constraint is CoWoS, which stands for Chip-on-Wafer-on-Substrate and which is essentially a very expensive way of gluing GPU dies to stacks of high-bandwidth memory on a shared silicon interposer. Every single Vera Rubin module needs it. Every Blackwell module already needs it. Every AMD MI400-series module needs it. TSMC is the only company on Earth that can do it at the volumes the hyperscalers are committing to, and TSMC’s CoWoS lines have been the gating supply-chain constraint on the entire AI buildout for roughly the last 18 months.
Nvidia disclosed at Computex that Vera Rubin NVL72 racks pair 36 Vera CPUs with 72 Rubin GPUs over the sixth-generation NVLink Switch, with the company claiming up to 10x higher inference performance per watt and 10x lower cost per token relative to current Blackwell systems. Those numbers depend on actually shipping the chips. Shipping the chips depends on CoWoS. CoWoS depends on a TSMC capacity buildout that runs through 2027 and was already oversubscribed before any of these announcements happened.
So Huang’s trip was, in effect, asking TSMC to find more room in lines that are already full, for a customer that is already TSMC’s largest, for a product that the entire AI ecosystem is planning its 2027 capex around. It is the most polite emergency in semiconductors. The Computex keynote will be the slick part. The TSMC meeting was the part that determines whether any of the slick part actually exists by Q4.